JK Flip-Flop (Chip)

The JK flip-flop can save the actual input states like the d flip-flop upon triggered by the clock input. If the input J is 1 (high) and K is 0 (low) during a clock pulse, the output becomes 1 (high). If J is 0 (low) and K is 1 (high) during the pulse, the output becomes 0 (low). If both inputs are 0 (low) during the clock pulse, the state is maintained. If both inputs are 1 (high) the input is toggled if a rising edge was detected at the clock input.

If no signals are wired to either the J or the K input, these inputs are read as 1 (high). This is done by internal pull-up resistors that pull the signal to low in the absence of an input signal. This has as result that the JK flip-flop toggles it's output value on each positive clock edge.

If no signal is connected to an input pin, the input is read as 0 (low). This is done by internal pull-down resistors that pull the signal to low in the absence of an input signal. Using this mechanism the NOR gate can be used with 2 or 3 inputs in the exact same way.

Play with the 2 switches and the button to get an understanding how the JK flip-flop actually works.